1. Field of the Invention
The invention relates to a method of fabricating a flash memory device and, more particularly, to a method of fabricating a flash memory device in which a program characteristic can be improved and the leakage current can be reduced.
2. Discussion of Related Art
In stacked gate type flash EEPROM devices, when cells are driven, pinch off is generated in the gate to drain the overlap region as the depletion region of the drain junction region shrinks. The strong electric field so generated accordingly generates hot carriers, and electrons of the hot carriers accumulate on the floating gate.
FIGS. 1A to 1C are cross-sectional views illustrating process steps of a method of fabricating a flash memory device in the related art. FIG. 1 shows a junction formation process of a cell region and a high voltage PMOS transistor formation region.
As shown in FIG. 1A, a tunnel oxide layer 11 is formed on a semiconductor substrate 10 in which an active region is defined by an isolation film (not shown). A cell transistor gate in which a floating gate 12, a dielectric layer 13, and a control gate 14 are stacked is then formed in the cell region. A PMOS transistor gate in which conduction layers for the floating gate 12 and the control gate 14 are stacked is formed in the high voltage PMOS transistor formation region.
Thereafter, a first source junction 15 is formed by a source ion implant process employing a cell source mask, and an annealing process is then implemented.
Though not shown in the drawings, a Double Doped Drain (DDD) ion implant process is then performed on the high voltage NMOS transistor formation region.
A first photoresist PR1 through which the high voltage PMOS transistor formation region is exposed is then formed. A DDD ion implant process using the first photoresist PR1 as a mask is carried out on the high voltage PMOS transistor formation region, thus forming first and second P− junctions 16, 17 within the semiconductor substrate 10 on both sides of the PMOS transistor gate. The first photoresist PR1 is then stripped.
A common source line is then formed by a Self Aligned Source (SAC) etch process, an ion implant process, and an annealing process.
As shown in FIG. 1B, a second photoresist PR2 through which the cell region is exposed is then formed. A cell source/drain ion implant process is then performed to form a second source junction 18 and a drain junction 19. The second photoresist PR2 is then stripped.
With reference to FIG. 1C, an insulating layer (not shown) is deposited on the entire structure. The insulating layer is etched back to form spacers 20 on both sides of the cell transistor gate and the PMOS transistor gate.
Though not shown in the drawings, a junction region is formed in the high voltage NMOS transistor formation region. A third photoresist PR3 through which the high voltage PMOS transistor formation region is exposed is formed. A P+ ion implant process is performed to form first and second P+ junctions 21, 22 within the first and second P− junction 16, 17, respectively. The third photoresist PR3 is then stripped.
In the stacked gate type NOR flash device constructed above, about ten kinds of transistors are used, in terms of device characteristics. This requires many processes in forming the junctions of each transistor. For this reason, before the gates are formed, several threshold voltage ion implant processes must be performed in order to satisfy the threshold voltage of each transistor. The threshold voltage ion implant process and the junction ion implant process are necessarily required in terms of device characteristics.
As the gate length reduces below the sub micron level, however, a leakage current is generated between the source and drain junctions of the cells, and a program characteristic is degraded accordingly. To compensate for the degradation of the program characteristic, a cell threshold voltage ion implant process dosage is increased. If the dosage is increased, the cell threshold voltage rises and the cell current can be lowered accordingly.
As there is a tendency in which the gate length reduces below the sub micron level, leakage occurs between the source junction and the drain junction, thereby degrading a program characteristic.
To compensate for the degradation of the program characteristic, a threshold voltage ion implant process is performed. It is, however, very difficult to solve the leakage problem occurring between the source junction and the drain junction through this process. That is, to reduce the leakage problem between the source junction and the drain junction of the cell, the dose of the threshold voltage ion is increased. If the dose is increased as described above, the threshold voltage of the cell rises and the cell current is lowered accordingly. In addition, a disadvantage in which the cell current is lowered out weights an advantage in which the program characteristic is improved. Accordingly, there are no significant advantages.
To solve the above-mentioned problems, a method of adding ions to the channel region of the cell or changing the junction structure has been used. However, these methods increase the process step number and raise the manufacturing cost.